Firstly the 1’s complement of B is obtained by the NOT gate and 1 can be added through the carry to find out the 2’s complement of B.This operation considers that the addition of minuend along with the 2’s complement of the subtrahend is equal to their subtraction.As shown in the figure, the parallel binary subtractor is formed by combination of all full adders with subtrahend complement input.The parallel subtractor can be designed in several ways including combination of half and full subtractors, all full subtractors or all full adders with subtrahend complement input. The process continues till the last full adder FAn uses the carry bit Cn to add with its input An and Bn to generate the last bit of the output along last carry bit Cout.Ī Parallel Subtractor is a digital circuit capable of finding the arithmetic difference of two binary numbers that is greater than one bit in length by operating on corresponding pairs of bits in parallel.Next, the full adder FA2 uses this carry bit C2 to add with the input bits A2 and B2 to generate the sum S2(the second bit of the output sum) and the carry C3 which is again further connected to the next adder in chain and so on.As shown in the figure, firstly the full adder FA1 adds A1 and B1 along with the carry C1 to generate the sum S1 (the first bit of the output sum) and the carry C2 which is connected to the next adder in chain.Learn all GATE CS concepts with Free Live Classes on our youtube channel. Practice GATE exam well before the actual exam with the subject-wise and overall quizzes available in GATE Test Series Course. ISRO CS Syllabus for Scientist/Engineer ExamĪttention reader! Don’t stop learning now.ISRO CS Original Papers and Official Keys.GATE CS Original Papers and Official Keys.

4 bit parallel adder